1. Field of the Invention
The present invention relates generally to a high speed flip-flops, and more specifically to high speed current mode flip-flops for use in communication systems.
2. Description of the Related Art
High speed flip-flops, or data latches, are key circuits in serial digital communications applications. The receiver of a high speed serial communication link typically pushes newly received data bits into a shift register, which is made up of many individually linked data latches. Although data is received serially, the internal core circuitry of a device typically manipulates data in bit groups of predefined size (i.e. byte, word, etc.). Therefore, when a predetermined number of latches in the shift register have received data, the received data in the shift register is typically output in parallel onto a bus for further processing. Similarly, when a transmitter is coupled to a serial communication link, a group of data bits is loaded in parallel into a shift register, and the loaded data is then serially shifted out one bit at a time onto the serial link via a signal output driver. Since registers, or latches, are an integral part of data reception and transmission operations, and since they need to operate at, or higher than, the transmission rate of the communication system, high speed latches, or flip-flops, are an integral part of any high speed communication system.
Thus in such communication systems, a high speed serial data stream is converted into a multi-bit parallel bus using multiple flip-flops configured such that the flip-flops are either used as a shift register or a parallel load/unload register. The dual operation, or configuration, where a multi-bit parallel bus is converted into a high speed serial data stream is just as frequently used since a typical bidirectional communication system is just as likely to transmit data as it is to receive it. Both of these register applications involve a multiplexor coupled to the data input of the flip-flop, or latch. This combination of multiplexor and flip-flop is thus very common in such communication applications. Additionally, since the speed of the flip-flop dictates how fast data can be received, or transmitted, typically the speed of this circuit limits the speed of the serial communication path.
The highest frequency of operation for this type of digital design can generally be achieved by using a differential current steering logic family, such as CMOS current mode logic, CML. Differential logic families typically use two leads to transmit two sub-signal components that together constitute a complete signal. That is, a differential signal consists of both the logic true and logic complement form of a signal carried on two separate leads. The signal information may be read by coupling the two leads to the inputs of a differential amplifier, which determines which of the two leads is at a higher potential. By discerning which of the two leads is at a higher potential, one can determine if the leads carry a logic high data signal or a logic low data signal. This is in contrast to traditional single-ended transmissions, which carry signal information on a single lead and data signal information is determined by checking the voltage level on the lead to resolve whether it is at a high enough potential to represent a first logic level or at a low enough potential to represent a second logic level. Since information on a differential signal is conveyed by setting one lead of a two-lead pair to a higher potential then the other, it is not necessary that the leads be raised or lowered to potential levels traditionally associated with a logic high or logic low signal in single-ended technology. Therefore, the voltage swings on a differential signal are much smaller, and thus much faster.
Although a differential signal requires two leads to represent one signal (a first lead to carry the logic true form of the signal and a second lead to carry the logic complement form of the signal), for the sake of brevity, part of the following discussion will reference only the differential signal (and not the two leads necessary for conveying the signal) when discussing differential communication systems, with the understanding that the one signal requires two leads for proper conveyance. Two sub-signal components, a true and a complement, will be used as necessary, when such use facilitates understanding of a particular feature. For now, it suffices to say that current mode logic is characteristically a differential signal technology.
Many configurations of current mode logic (CML) are known, and they are typically distinguished by the style of load device used and the number of current sources. Current mode logic, however operates on the concept of steering current; current steered one way produces a first logic level, and current steered another way produces second logic level. Since logic content is determined from the direction of current flow, current must necessarily be constantly flowing when a device is operational. As a result, CML circuitry, although fast, consumes more current and thus more power than static CMOS circuitry, which consumes current only during logic transitions. That is, CML topologies typically have inferior speed-to-power ratios than do static CMOS topologies, but offer a maximum operating frequency several times higher than static CMOS topologies. Therefore, CML is still preferred for very high frequency applications, such as high speed communication systems.
A compromise for obtaining high speed performance with reduced power requirements is to combine both CML and static CMOS technologies. The portions of a circuit that have the highest speed requirements are identified and implemented using a CML topology, and the remaining, slower portions of the circuit are implemented using a static CMOS topology. For example in the case of high speed communications, the portions with the highest speed requirements are implemented using current steering digital logic circuits, and the slower portions are implemented using static CMOS circuitry. In either case, the CML portion of the circuitry still places a large demand on power sources.
Therefore, any reduction in the power requirements of the current steering digital logic circuits would reduce the total power of the highest speed portion of a system, such as a serial communication system. As stated above in regards to serial communications systems, one the most commonly needed circuit components are high speed latch circuits and multiplexers since they are integral to reception and transmission operations. Thus, the need for reducing the power requirements of high speed latch circuits and multiplexors in CMOS CML devices is self evident. Lower power CML latch circuits and multiplexers would increase the operating frequency of high speed serial communications systems while reducing their total power requirements.
One type of latch most commonly used in communication systems is the master-slave latch, which is comprised of two separately clocked latches, or flip-flops. With reference to FIG. 1, a multiplexor, MUX, 11 selects from among two independent signals A and B, in accordance with a selection input A/B, and the selected input signal A_or_B is passed to master-slave latch 13, which is comprised of a master latch 31a and a slave latch 33b. In the present example, it is assumed that MUX 11 and master-slave latch 13 are both implemented in CML technology. Therefore, although only one signal line is shown for the sake of clarity, it is to be understood that each signal line is comprised of two sub-signal components on two leads. Thus, both signal A and signal B consist of two separate leads, each carrying respective true and complement sub-signal components. Similarly, signal A_or_B coupling MUX 11 to master-slave latch 13 should be understood to consist of two leads, a true A_or_B sub-signal component and a complement A_or_B sub-signal component. Likewise intermediate signal 15 and output signal Out also consist of two leads carrying complementary sub-signal components.
In the present example, only features of interest of a CML implementation are shown. A more detailed view of a CML based latch can be found in U.S. Pat. No. 6,798,249 to Wong et al. In the present case, it suffices to point out that a key feature of a CML topology is the use of a pull-up load and a current source. For example, load 17 couples CML switching MUX circuit 11a to Vcc, and CML switching MUX circuit 11a is supplied current by current source 21. Similarly, master latch 31a includes load 32 and current source 36, and slave latch 33b includes load 34 and current source 38. Information is conveyed by the direction in which current supplied by a respective current source is steered within an individual CML switching circuit.
For example, information regarding whether signal A or signal B is conveyed to output A_or_B is determined by the path the current from current source 21 takes within MUX 11.
Typically, each CML device component has its own pull-up load and its own current source. Of particular interest is that a typical master-slave latch typically includes two latches 31a and 33a. The first latch 31a includes what is typically designated a master latch 31 since it typically latches data during the first phase of a clock cycle. The second latch 33a includes what is typically designated a slave latch 33 since it typically latches data during the second phase of the clock cycle and its data contents are dictated by the master latch 31. Since a typical master-slave latch 13 includes two separate latches, 31a and 33b, each of the two latches has a respective pull-up load 32 and 34, and a respective current source 36 and 38. Since both latches 31a and 33b typically have identical latch architecture, the values of pull-up loads 32 and 34 are typically equal, and the magnitudes of the current provided by current sources 36 and 38 are the same. A basic difference between latch 31a and 33b is that each is responsive to opposite phases of the clock signal.
In the present example, the master latch 31 is responsive to the true clock signal, CK, and the slave latch 33 is responsive to the complement clock signal CK_C. In this manner, it is assured that a first latch, either 31 or 33, latches in data during a first half of the clock (i.e. a first phase of the clock) while the second latch maintains its current output constant, and the second latch latches in new data (output of the first latch) during a second half of the clock (i.e. a second phase of the clock) while the first latch maintains it current output constant.
Therefore in the present example, when signal CK goes high, master latch 31 responds by accepting whatever data is on signal A_or_B and conveying the accepted data to its intermediate output 15. Although intermediate output 15 is coupled to the input of slave latch 33, slave latch 33 is not affected by changes on intermediate output 15 since the complementary clock, CK_C, is low and slave latch 33 therefore maintains its output constant and does not accept new input data.
When clock signal CK goes low and complementary clock signal CK_C goes high, master latch 31 responds by latching in and holding its intermediate output 15 steady at the same logic value as when clock signal CK went low. Any further changes in signal A_or_B while signal CK is low are ignored by master latch 31. Conversely, when signal CK went low, complementary signal CK_C went high causing slave latch 33 to begin accepting input data on intermediate output 15 and conveying the accepted data to its output signal, Out. Upon signal CK returning high, complementary signal CK_C goes low causing slave latch 33 to latch and hold the output data level at the time when complementary signal CK_C went low. In this way, master latch 31 can accept new data while slave latch 33 holds current data steady until it is time to update the output of slave latch 33.